About us:

Mythic has developed a unified hardware and software platform featuring its unique Mythic Analog Compute Engine (Mythic ACE™) to deliver revolutionary power, cost, and performance that shatters digital barriers preventing AI innovation at the edge. Mythic's unique technology makes it much easier and more affordable to deploy powerful AI solutions, from the data center to the edge device. The company has raised over USD 125M in a recent funding round and has offices in Palo Alto (CA, USA), Austin (TX, USA), and Bangalore (Karnataka, India).

About This Role:

Mythic is a fast-paced startup looking for individuals that enjoy wide-reaching and flexible roles. The primary responsibility for this position is implementaiton of DFT features on Mythic's chips.

You will lead end-to-end Design for Testability (DFT) implementation, verification for complex ASIC/SoC designs. You will own all aspects of DFT for SoC such as MBIST, IJTAG, Scan and ATPG .

You will also contribute significantly to DFT methodologies to establish flow for all DFT features like MBIST,SCAN and ATPG and enable first-pass success of these chips. You are expected to be involved and contribute to every phase of the design cycle from Concept to Silicon.

Beyond DFT for our novel chip architecture, this role also presents a unique opportunity to get involved with and learn more about state-of-the-art deep neural networks (DNNs). You will also be collaborating with the RTL design , Physical design, STA and analog design teams at Mythic.

• BS/MS/PhD in EE/ECE
• At least 8+ years of industry experience
• SoC level experience in DFT methodologies (e.g. Memory Repair, Hierarchical DFT, IEEE 1687 iJTAG, Scan, ATPG, Memory BIST.
• Experience with SoC Level DFT Integration, Verification, DFT test suite development and RTL design for DFT.
• Experience with SoC Level DFT Integration, Verification and RTL design for DFT
• Experience with DFT strategies like Scan insertion, TPI, SSN, Hierarchical DFT and ATPG
• Pre-Silicon test planning & verification strategy
• Knowledge & experience of low power concepts, clock gating, power gating is a plus
• Adept at root cause analysis and resolving DFT implementation issues
• Must have good communication skills and the ability to work in a worldwide team environment
• A past experience of working on an AI processor design is a huge plus.

• Experience working at startups
• Knowledge of Low power DFT solutions
• Experience of working with STA team to define DFT timing constraints
• Working with ATE (Automatic Test Equipment) for bring-up, debugging, and yield improvement
• Proficiency in Synopsys (TetraMAX/DFT Compiler) or Siemens/Mentor (Tessent) tools, Verilog/SystemVerilog
• Good script skills including Perl, Tcl, Python, etc.

• Knowledge of chiplet-based design limitations and their impact on physical design.
• Experience in Sub-10nm designs
• Familiarity and hands-on experience with Cadence toolsets.